Mitigating FPGA Obsolescence Using Microcircuit Emulation

FPGA Obsolescence Solutions

Before jumping into our solutions for mitigating FPGA Obsolescence Using Microcircuit Emulation, lets review the current capabilities that we have. Our existing 0.8µm CMOS Emulation technology is compatible with following FPGA families: •Actel: ACT1, ACT2, ACT3 •Xilinx: XC2000, XC3000, XC3100A, XC4000, XC4000A, XC4000E •Altera:  FLEX8000, MAX5000, MAX7000, MAX9000

These families use a +5.0V supply voltage.    We are also working on 0.35 µm CMOS Emulation technology, which will enable  us to start Emulating FPGA devices that use a +3.3V supply.   Stay tuned for more information on upcoming releases. Remember, GEM does not provide un-programmed “blanks.”   GEM provides the altered/programmed version, or a hard coded ASIC version. BENEFITS The FPGA Emulation solution provides a permanent source for Form-Fit-Function-Interface (F3I) programmed FPGA-equivalent components for use in Military systems. Our FPGA to ASIC design-porting strategy is a proven method to support the Warfighter.

 

FPGA Replacement: Getting Started

Requests for quotes may be made directly through the website, or through your DLA logistics channels.    

When requesting assistance with an FPGA you will receive an FPGA checklist as shown below.  This will help SRI  determine if the FPGA is “GEMable” and the level of effort required to provide a GEM replacement.   At a minimum, we will need a performance specification (data sheet), programmed sample units, and a programming file,  but the more information you can provide the better as this will decrease the amount of reverse engineering necessary and improve lead-time.

As you can see maintaining proper material and records (technical data package) is essential for mitigating obsolescence!

 

Mitigating FPGA Obsolescence Using Microcircuit Emulation

THE NEED

Field Programmable Gate Arrays (FPGAs) are widely used throughout the defense industry as a critical component in systems.  These components are user programmable, allowing the engineers to program in a design tailored to the functionality of a specific board or system.  These devices can support complex designs and interface with other components through various I/O standards.  FPGAs also give the designers flexibility in the event of  a unique requirement or unexpected design changes.  As technology advances, older FPGAs become obsolete as faster and more advanced device families are introduced.  However, there are still military systems in the field that require replacement parts for these obsolete FPGAs.  While FPGA vendors may recommend using a newer FPGA to replace ones that are going obsolete, they are not a suitable replacement for existing board designs as they are not Form-Fit-Function-Interface (F3I) compatible.

 

THE EMULATION SOLUTION

DLA and the AME Program have developed a flow to Emulate FPGAs as Application Specific Integrated Circuits (ASICs).  This involves taking the exact design implemented on the FPGA and targeting it to one of the Emulation gate arrays to produce an ASIC form of the design.  The resulting part is not reprogrammable, but it will otherwise be form-fit-functionally equivalent to the device as programmed for use in a specific system location.

One difficulty in Emulating FPGAs is that the customer often does not have all the design information needed to reproduce the part, and the only piece of information available is the programming file used to configure the FPGA and/or PROM.  Therefore, we have established a flow utilizing the reverse engineering capabilities of Macaulay-Brown, Inc. to take an FPGA programming file and/or PROM, and extract the design information (source code or netlist).

Macaulay-Brown, Inc. (an Alion company) has developed the capability to do this for several generic FPGA families. including embedded memories and math blocks.  These macrocells will be implemented in the converted netlist during synthesis.  Once the netlist conversion is complete, the design is run through several tools to insert testing capabilities and perform place and route.  The final post route design is analyzed to verify timing and functionality before it is released to fabrication.  When a netlist is extracted, it can then be targeted to one of the existing GEM gate arrays.

To help with the conversion, we developed a library of macrocell components that are common among FPGAs including embedded memories and math blocks.  These macrocells will be implemented in the converted netlist during synthesis.  Once the netlist conversion is complete, the design is run through several tools to insert testing capabilities and perform place and route.

The final post route design is analyzed to verify timing and functionality before it is released to fabrication.  To verify the functionality and characteristics of the final part against the original FPGA device, test boards are designed for each of the components so that they can be tested using the ATE.  The test team has developed a flow to convert simulation waveforms into test vectors that can then be applied to the devices.  This will be essential for FPGA designs as they have more complex functionality that will need to be exercised.  The test engineers can run the functional test vectors on both the ASIC and FPGA to verify that the designs are functionally equivalent and meet the required specifications before delivering to the customer.

You can download some of this information here.