Base Wafers and Gate Arrays

Base Wafers and Gate Arrays

• The DLA Emulation programs utilizes a split manufacturing process

• “Base” or front-end-of-line (FEOL) wafer processing

• A batch of gate array wafers are processed through the majority of the  manufacturing flow with predefined circuit elements and held in inventory before metallization

• “Personalization” or back-end-of-line (BEOL) processing

• For each new part order, a wafer is taken from inventory and processed through metal interconnect processing to create the final microcircuit

• Benefits of the split manufacturing process

• Minimizes wafer production time for emulated devices

• Allows for Integrated Circuits (ICs) originally manufactured in diverse technologies to be produced from a managed inventory of standardized base wafers

An overview of the GEM Production System for emulating microcircuits is illustrated below

• Technologies oPered by the Emulation Programs have been expanded over time

• TTL (Transistor Transistor Logic) 5-Volt logic families (S, LS, ALS, FAST, etc.)

• ECL (Emitter Coupled Logic) devices (10H, 10K)

• CMOS logic devices with power supplies from 3.3 V up to 20 V

• Complex ASIC

• Programmable logic arrays (PLA, PAL, GAL, CPLD & FPGA )

• Implemented as hard-coded (non-reprogrammable) ASICs

• Memory devices

The table below highlights the available Emulation technologies by process technology, and example applications