The design of the Emulation circuit utilizes modern CAD tools. Development of transistor models and cell libraries is done for every Emulation technology. This information is used in the circuit design flow to guarantee best performance over process, voltage and temperature corners. In addition, SPICE and Logic simulations, together with available original part data, are used to check timing and centering current/voltage matching to ensure conformance with the required electrical and delay parameters. An electronic schematic and/or HDL (VHDL or Verilog) model is created and validated based on the functional verification developed during reverse engineering. After the circuit design is completed the physical interconnection is laid out and verified.
Our in-house design center works closely with our Trusted foundry and using advanced TCAD tools to analyze the fabrication process, enables the unique capability for SRI to meet our customers’ requirements. Our digital design capability covers a range of technologies (CMOS, BiCMOS, Bipolar) and feature sizes, from 3.0 µm down to 0.35 µm. Our current development thrust is to add a High Voltage Analog capability.
SRI design engineers and layout personnel use a suite of CAD tools to develop compliant Emulation designs. These are listed below.
- Schematic Capture
- SPICE simulation
- Behavioral Simulation
- Static Timing Analysis
- Fault coverage vector generation
- Fault Coverage Analysis
- Design-for-Test (DFT)
- EM/IR Thermal reliability
- Power Integrity
- Place and Route
- Layout capture
- Layout verification LVS/DRC/ERC
- Interconnect parasitic extraction
Back-annotation, simulation and analysis metrics guarantee the part design meets functional and speed performance after fabrication. High fault-coverage and high toggle-coverage metrics guarantee a high degree of testability that complies with and expands on the original device specifications. This ensures SRI designers have meet the required device specification or drawing on the first pass.