The SRI Microcircuit Emulation Center (MEC) integrated circuit (IC) design & layout group has provided custom circuit solutions for over 35 years in support of the Defense Logistics Agency (DLA) Generalized Emulation of Microcircuits (GEM) and Advanced Microcircuit Emulation (AME) programs. The QML-certified center maintains a Quality Management Plan to conform to the requirements of MIL-PRF-38535 and MIL-STD-883 for all aspects of circuit design, layout validation, and verification.

The design & layout group uses a state-of-the-art suite of Electronic Design Automation (EDA) tools that to design Digital and Analog ICs on all the processes currently available from SRI’s Microcircuit Emulation Wafer Foundry as well as any future process developments. The devices in all the production processes are completely modeled to ensure the manufactured design is functionally correct and will be in full conformance with customer specifications. The design libraries for each process are completely characterized over the full military voltage and temperature ranges.

The design & layout group has experience designing Digital and Analog ICs. The current production processes provide the capability to design circuits with a dozen bipolar transistors through advanced complex microcircuits with millions of NMOS and PMOS transistors. The design flow can handle the synthesis and mapping of any combination of in-house and externally generated logic cores onto our processes. Layout of the designs are performed either by hand or by using advanced place & route tools. The parasitic capacitance and resistance of the back-end-of-line (BEOL) process is characterized to create back annotated netlists to verify the IC will perform to specification when manufactured. Our capability to design Op Amps, comparators and regulators up to 20 V leverages recent process developments and will be further extended to cover higher voltage Analog ICs.

The table shows a simplified list of EDA capability is as follows:


  • Netlist development and simulation
    Schematic capture
    SPICE simulation
    Behavioral simulation
    Static timing analysis
    Cell characterization
    Fault coverage vector generation
    Fault coverage analysis
    Design-for-test (DFT)
    Formal Equivalence Check
Design&Layout Flowchart


  • Place and route
  • Layout capture
  • Layout verification LVS/DRC/ERC
  • DRC Deck Generation
  • Interconnect parasitic extraction
  • IR/Thermal/Power/EM Analysis

The DLA Emulation programs maintain a Controlled Unclassified Information (CUI) compliant network cluster of Linux workstations and servers to support high uptime and availability of EDA software and data. All data are backed up daily and off-site storage is used to guard against data loss. The EDA software is regularly updated and expanded as new processes, technologies, and capabilities become available.

The MEC Design Center works closely with our on-site Trusted foundry and uses advanced TCAD tools to analyze the fabrication process. This enables SRI the unique capability to meet customers’ requirements. Our digital and analog design capability covers a range of technologies (CMOS, BiCMOS, Bipolar) and feature sizes, from 3.0 μm down to 0.35 μm. Our current development thrust is to add 40 V Analog capability.